Image sensor and method for manufacturing the same

ABSTRACT

An image sensor including a substrate, a trench isolation, a plurality of image sensing units, at least one phase detection unit, and an interconnection layer is provided. The trench isolation is in the substrate, and a plurality of active areas of the substrate are separated from each other by the trench isolation. The image sensing units and the at least one phase detection unit are in the active areas arranged in an array, and a sensing area of the at least one phase detection unit is smaller than a sensing area of each of the image sensing units. The interconnection layer is disposed on the image sensing units and the at least one phase detection unit. In addition, a method of fabricating an image sensor is also provided.

BACKGROUND

Compared to charge coupled device (CCD) sensors, a CMOS image sensor hasmany advantages such as low voltage operation, low power consumption,compatibility with logic circuitry, random access, and low cost. Amongthe CMOS image sensors, a phase detection auto-focus (PDAF) CMOS imagesensor is widely used. The PDAF CMOS image sensor adapted photodiode inconjunction with metal grids disposed thereon to render phase detection,thereby achieving a focus function.

The current isolation method for adjacent photodiodes is mostly implantisolation. However, implant isolation is not sufficient to eliminate thecross-talk effect between adjacent photodiodes, and the sensitivity ofthe PDAF CMOS image sensor is compromised.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flow chart illustrating a method of fabricating an imagesensor in accordance with some embodiments.

FIGS. 2A-2J are cross-sectional views illustrating a manufacturingprocess of an image sensor in accordance with some embodiments.

FIG. 3 is a perspective top view of a region of the image sensor of FIG.2E.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a flow chart illustrating a method of fabricating an imagesensor in accordance with some embodiments. FIGS. 2A-2J arecross-sectional views illustrating a manufacturing process of an imagesensor in accordance with some embodiments.

Referring to FIG. 1 and FIG. 2A, a substrate 102 having a plurality ofactive areas 106 separated from each other are provided in Step S001.Specifically, the substrate 102 has a first surface 102 a and a secondsurface 102 b opposite to the first surface 102 a. A plurality ofinsulators 104 are formed in the substrate 102 and extend from the firstsurface 102 a of the substrate 102 toward the interior of the substrate102. In other words, the insulators 104 are formed to be embedded in thesubstrate 102. The insulators 104 have difference sizes, and thusbetween two adjacent insulators 104, an opening OP1 is formed. In otherwords, among the insulators 104, multiple openings OP1 having differentsizes are formed to constitute the active areas 106 arranged in anarray. Specifically, due to the difference in the size of the openingsOP1 of the insulators 104, the active areas 106 would also have at leasttwo different sizes. In some embodiment, the insulators 104 are shallowtrench isolation (STI) structures. However, the present disclosure isnot limited thereto. In some alternative embodiments, other insulatingmaterial may be adapted as the insulator to separate the active areas106. The formation process of the insulators 104 (i.e. the STIstructures) may be attained by the following steps. First, a pluralityof shallow trenches having a predetermined depth are formed in thesubstrate 102 by photolithograph/etch process or other suitablepatterning processes, for example. Next, a dielectric layer is depositedin the trenches. Subsequently, a portion of the dielectric layer isremoved (e.g., polishing, etching, or a combination thereof) to form theinsulators 104 (i.e. the STI structures). A material of the substrate102 includes silicon, and a material of the insulators 104 (i.e. the STIstructures) includes silicon oxide, silicon nitride, silicon oxynitride,other suitable materials, or a combination thereof. In some alternativeembodiments, the substrate 102 may be made of some other suitableelemental semiconductor, such as diamond or germanium; a suitablecompound semiconductor, such as gallium arsenide, silicon carbide,indium arsenide, or indium phosphide; or a suitable alloy semiconductor,such as silicon germanium carbide, gallium arsenic phosphide, or galliumindium phosphide. In addition, in some embodiments, the substrate 102has a thickness of about 1.5 to about 3 μm.

Referring to FIG. 1 and FIG. 2B, in Step S002, a plurality of imagesensing units 204 and phase detection units 202 are formed in the activeareas 106. In some embodiments, the image sensing units 204 and thephase detection units 202 are formed through ion implantation on thefirst surface 102 a of the substrate 102. For example, the image sensingunits 204 and the phase detection units 202 are photodiodes, whereineach of the photodiodes may include at least one p-type doped region, atleast one n-type doped region, and a p-n junction formed between thep-type doped region and the n-type doped region. In detail, when thesubstrate 102 is a p-type substrate, n-type dopants, such as phosphorousor arsenic, may be doped into the active areas 106 to form n-type wells,and the resulting p-n junctions in the active areas 106 are able toperform the image sensing function and phase detection function.Similarly, when the substrate 102 is an n-type substrate, p-typedopants, such as boron of BF₂, may be doped into the active areas 106 toform p-type wells, and the resulting p-n junctions in the active areas106 are able to perform the image sensing function and phase detectionfunction. Detailed descriptions of ion implantation processes forforming n-type doped regions (wells) or p-type doped regions (wells) areomitted herein. In some alternatively embodiments, the image sensingunits 204 and the phase detection units 202 may be other photoelectricelements capable of performing image sensing and phase detectionfunction. When a reversed bias is applied to the p-n junctions of theimage sensing units 204 and the phase detection units 202, the p-njunctions are sensitive to an incident light. The light received ordetected by the image sensing units 204 and the phase detection units202 is converted into photo-current such that analog signal representingintensity of the photo-current is generated.

As mentioned above, since the active areas 106 of the substrate 102 havedifferent sizes, the photodiodes formed in the active areas 106 alsohave different sizes. For instance, a size of each of the image sensingunits 204 is larger than a size of each of the phase detection unit 202.In particular, the image sensing units 204 have a width W1 and the phasedetection units 202 have a width of W2, and as illustrated in FIG. 2B,width W1 is greater than width W2. In some embodiments, lengths of theimage sensing units 204 and the phase detection units 202 are identical,and under the said circumstance, a sensing area A1 of each of the imagesensing units 204 is greater than a sensing area A2 of each of the phasedetection units 202. It should be noted that the lengths of the imagesensing units 204 and the phase detection units 202 may be different insome alternative embodiments, as long as the sensing area A2 is smallerthan the sensing area A1 of the image sensing units 204. Moreover, insome embodiments, the substrate 102 is exemplified to encompass multiplephase detection units 202, but it construes no limitation in thedisclosure. In some alternative embodiments, one single phase detectionunit 202 may be sufficient.

After formation of the image sensing units 204 and the phase detectionunits 202, a logic circuit may be formed on the substrate 102. The logiccircuit is designate for receiving and processing signal originated fromthe image sensing units 204 and the phase detection units 202. The logiccircuit, for example, includes conductive traces and NAND/NOR gates. Amaterial of the logic circuit may include, but not limited to, metal andpolysilicon. It should be noted that the location of the logic circuitis not limited on the substrate 102. In some alternative embodiments,the logic circuits may be fabricated on other elements formedsubsequently, and the explanations will be discussed later.

Referring to FIG. 1 and FIG. 2C, in step S003, an interconnection layer300 is formed on the first surface 102 a of the substrate 102. Theinterconnection layer 300 is in contact with the image sensing units 204and the phase detection units 202 such that signal generated from theimage sensing units 204 and the phase detection units 202 may betransmitted to other components for processing. For example, analogsignal generated from the image sensing units 204 and the phasedetection units 202 is transmitted by the interconnection layer 300 toother components, such as an analog-to-digital converter (ADC), forprocessing. In some embodiment, the interconnection layer 300 includestrace layers 302, 304, and a bonding substrate 306, but they construe nolimitation in the disclosure. In some alternative embodiments, certainforegoing layers within the interconnection layer 300 may be omitted, aslong as the signal of the image sensing units 204 and the phasedetection units 202 are able to be transmitted to other components forprocessing.

In some embodiments, the trace layer 302 is in contact with and/orelectrically connected to the image sensing units 204 and the phasedetection units 202. Another trace layer 304 is formed on the tracelayer 302, and is electrically connected to the trace layer 302.Suitable material for the trace layers 302, 304 includes conductors suchas metal. It should be noted that the trace layer 302 and the tracelayer 304 may be made of a same material or different materials, and mayinclude a singe layer of metallic traces or multiple layers of metallictraces. In a scenario where multiple layers of metallic traces are foundin the trace layers 302, 304, interlayer dielectric layers (ILD) areinserted between each metallic trace layer. A material of the ILD layerincludes silicon oxide, silicon nitride, silicon oxynitride,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-onglass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide(e.g., SiCOH), polyimide, and/or a combination thereof. The bondingsubstrate 306 is disposed over the trace layer 304. In some embodiments,the bonding substrate 306 may be a blank substrate for enhancing themechanical strength of the device while serving as a protection layer.In some alternative embodiments, the bonding substrate 306 may includesmetallic traces located thereon for signal transmission. For example, asmentioned above, instead of forming the logic circuit on the substrate102, the logic circuit may be formed on the bonding substrate 306 insome embodiments.

Subsequently, as illustrated in Step S004 of FIG. 1 and FIG. 2D, a stepof thinning the substrate 102 is performed. In some embodiments, a backpolishing process of the substrate 102 is performed to reduce thethickness of the substrate 102. In other words, the second surface 102 bof the substrate 102 opposite to the interconnection layer 300 ispolished. The method for back polishing includes mechanical polishing orchemical polishing. For example, in some embodiments, the back polishingis achieved by chemical mechanical polishing (CMP), and in somealternative embodiments, the back polishing is attained by chemicaletching. The disclosure does not construe the polishing method, as longas the substrate 102 is polished to render a desired thickness.

Next, the substrate 102 is turned over such that the second surface 102b of the substrate 102 faces upwards. A trench isolation 400 including aplurality of first trench isolation patterns 402 and a plurality ofsecond trench isolation patterns 404 is formed in the substrate 102between active areas 106, as illustrated in Step S005 of FIG. 1 and FIG.2E. In Step S005, the trench isolation 400 is formed corresponding tothe insulators 104 (i.e. the STI structures shown in FIG. 2D) toseparate each of the image sensing units 204 and each of the phasedetection units 202. Unlike the insulators 104, the trench isolation 400extends from the second surface 102 b of the substrate 102 to the firstsurface 102 a of the substrate 102. In other words, the trench isolation400 penetrates through the substrate 102 and thus the trench isolation400 is deep trench isolation (DTI) in some embodiments. Processes forforming trench isolation 400 (i.e. DTI) are similar to the formationprocesses of the insulators 104, and the formation processes of thetrench isolation 400 (i.e. DTI) will be briefly described. Specifically,a plurality of deep trenches having a predetermined depth in thesubstrate 102 are first formed by photolithograph/etch process or othersuitable patterning processes, for example. For example, the trenchesmay extend from the second surface 102 b of the substrate 200 to theinsulators 104. Next, a dielectric layer is deposited in the trenches.Subsequently, a portion of the dielectric layer is removed to form thetrench isolation 400. In some embodiments, the dielectric layer isetched off to form the DTI. Similar to that of the insulators 104, amaterial of the trench isolation 400 includes silicon oxide, siliconnitride, silicon oxynitride, other suitable materials, or a combinationthereof.

FIG. 3 is a perspective top view of a region R1 of the image sensor ofFIG. 2E. Referring to FIG. 2E and FIG. 3, as mentioned above, the trenchisolation 400 includes first trench isolation patterns 402 and secondtrench isolation patterns 404. Each of the image sensing units 204 issurrounded by the first trench isolation patterns 402 and each of thephase detection units 202 is surrounds by both the first trenchisolation patterns 402 and the second trench isolation patterns 404.Specifically, in some embodiments, each of the image sensing units 204is adjacent to, or alternatively speaking, sandwiched by the firsttrench isolation patterns 402, and each of the phase detection units isadjacent to at least one of the second trench isolation patterns 404. Inother words, each of the image sensing units 204 is not adjacent to anyof the second trench isolation patterns 404. As mentioned above, theinsulators 104 structure have different sizes, and therefore the firsttrench isolation patterns 402 and the second trench isolation patterns404 disposed corresponding to the insulators 104 would also yielddifferences in size. Specifically, as illustrated in FIG. 2E and FIG. 3,an area A3 occupied by the second trench isolation patterns 404 islarger than an area A4 occupied by the first trench isolation patterns402.

Referring back to FIG. 1 and FIG. 2F, in step S006, an anti-reflectivecoating (ARC) layer 500 may be employed on the second surface 102 b ofthe substrate 102 to reduce the reflection of light. Specifically, amaterial of the ARC layer is, for example, silicon carbide (SiC),silicon nitride (SiN), or a high-k dielectric film. However, thedisclosure is not limited thereto. Other conventionally suitablematerial may also be adapted as a material for the ARC layer.

Subsequently, a dielectric layer 600 is formed over the ARC layer 500,as illustrated in Step S007 of FIG. 1 and FIG. 2G. The dielectric layer600 serves the function of isolating conductive materials. In someembodiments, the dielectric layer 600 includes low-k dielectricmaterials. It should be noted that the low-k dielectric materials aregenerally dielectric materials having a dielectric constant lower than3.9. Examples of low-k dielectric materials include BLACK DIAMOND®(Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphousfluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SILK®(Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) orfluorinated silicon oxide (SiOF), and/or a combination thereof. It isunderstood that the dielectric layer 600 may include one or moredielectric materials and/or one or more dielectric layers. In someembodiments, the dielectric layer 600 is formed to a suitable thicknessby Flowable CVD (FCVD), CVD, HDPCVD, SACVD, spin-on, sputtering, orother suitable methods.

Next, referring to FIG. 1 and FIG. 2H, in Step S008, a shieldingmaterial layer 700 a is formed over the dielectric layer 600 to shieldcomponents underneath thereof from an incident light. In someembodiment, the shielding material layer 700 a includes metal such astungsten, aluminum or other suitable reflective materials. Nevertheless,the material of the shielding material layer 700 a is not limitedthereto. Other opaque materials may be adapted as the material for theshielding material layer 700 a, as long as the material encompasses lowtransmittance with respect to the incident light.

Referring to FIG. 2H and FIG. 2I, the shielding material layer 700 a ispatterned to form a shielding grid layer 700, as illustrated in StepS009 of FIG. 1. In some embodiments, a mask material layer 800 is formedover the shielding material layer 700 a using processes such asspin-coating. The mask material layer 800 is sensitive to a specificexposure beam such as KrF, ArF, EUV or e-beam light. For example, themask material layer may be a photoresist made of a photosensitive resinor other suitable materials. In some embodiments, the mask materiallayer includes polymers, quencher, chromophore, solvent and/or chemicalamplifier (CA). Owing to the help of the photomask 800 a, aphotolithography process is performed on the mask material layer 800,and an etching process may be subsequently performed to pattern theshielding material layer 700 a. Specifically, the photolithographyprocess includes exposure, bake, and development, and the etchingprocess may include wet etching or dry etching.

Referring to FIG. 2I again, the shielding grid layer 700 is formed overthe dielectric layer 600. The shielding grid layer 700 includes aplurality of shielding grid patterns 702. In order for the incidentlight to reach the sensing area A1 of the image sensing units 204 andthe sensing area A2 of the phase detection units 202, the shielding gridpatterns 702 are not overlapped with the image sensing units 204 and thephase detection units 202. As illustrated in FIG. 2I, the shielding gridpatterns 702 completely shield the trench isolation 400 surrounding theimage sensing units 204 while partially shield the trench isolation 400surrounding the phase detection units 202. Alternatively speaking, asmentioned above, each of the image sensing units 204 is adjacent to thefirst trench isolation patterns 402, and each of the phase detectionunits is adjacent to at least one of the second trench isolationpatterns 404. Therefore, the shielding grid patterns 702 completelyshield the first trench isolation patterns 402 while partially shieldthe second trench isolation patterns 404. Moreover, between two adjacentshielding grid patterns 702, an opening OP2 is formed. Since theadjacent shielding grid patterns 702 are separated by substantially asame distance, among the shielding grid patterns 702, multiple openingOP2 having a substantially identical area A5 are formed. The area A5 ofthe openings OP2 of the shielding grid patterns 702 is substantiallyequal to the sensing area A1 of the image sensing units 204. On theother hand, the area A5 of the openings OP2 of the shielding gridpatterns 702 is notably larger than the sensing area A2 of the phasedetection units 202. Due to the fact that the area A5 of the openingsOP2 of the shielding grid patterns 702 is larger than the sensing areaA2 of the phase detection units 202, at least part of the second trenchisolation patterns 404 are overlapped with the openings OP2 of theshielding grid patterns 702. For instances, in some embodiments, anoverlapping percentage of the area A3 occupied by each of the secondtrench isolation patterns 404 and the area A5 of the openings OP2 of theshielding grid patterns 702 may be greater than 50% of the total area A5of the openings OP2 of the shielding grid patterns 702.

Thereafter, referring to FIG. 1 and FIG. 2J, in Step S100, a pluralityof micro-lenses 900 for focusing the incident light beams are formed onthe shielding grid layer 700 to complete the fabrication process of animage sensor 10. Each of the micro-lenses 900 includes a convex shapedupper surface which facilitates the convergence of the incident light,thereby enhancing the light received by the sensing area A1 of the imagesensing units 204 and the sensing area A2 of the phase detection units202. The micro-lenses 900 may be fabricated by materials such as silicondioxide or a resin material on intermediate transparent film.

In some embodiments, since the image sensing units 204 and the phasedetection units 202 are CMOS (Complementary-Metal-Oxide-Semiconductor)photodiodes, the image sensor 10 may be considered as a phase detectionauto-focus (PDAF) CMOS image sensor. Nevertheless, the disclosure is notlimited thereto. In alternative embodiments, the image sensor 10 may bea sensor of other forms. Moreover, since the sensing area A2 of thephase detection units 202 does overlap with the entire area A5 of theopenings OP2 of the shielding grid patterns 702, the phase detectionunits 202 are able to detect and calculate the direction of the incidentlight, thereby achieving a high sensitivity in focus function.Therefore, a CMOS image sensor with high pixel resolution may beattained. Moreover, due to the utilization of the trench isolation 400between the image sensing units 204 and the phase detection units 202,the cross-talk effect between adjacent image sensing units 204 and phasedetection units 202 is effectively reduced, thereby enhancing thesensitivity of the image sensor 10 as a whole.

In accordance with some embodiments of the present disclosure, an imagesensor includes a substrate, a trench isolation, a plurality of imagesensing units, at least one phase detection unit, and an interconnectionlayer. The trench isolation is in the substrate, and a plurality ofactive areas of the substrate are separated from each other by thetrench isolation. The image sensing units and the at least one phasedetection unit are in the active areas arranged in an array, and asensing area of the at least one phase detection unit is smaller than asensing area of each of the image sensing units. The interconnectionlayer is disposed on the image sensing units and the at least one phasedetection unit.

In accordance with alternative embodiments of the present disclosure, animage sensor includes a substrate, a trench isolation, a plurality ofimage sensing units, at least one phase detection unit, a shielding gridlayer, and an interconnection layer. The trench isolation is in thesubstrate, and a plurality of active areas of the substrate areseparated from each other by the trench isolation. The image sensingunits and the at least one phase detection unit are in the active areasarranged in an array. The shielding grid layer includes a pluralityshielding grid patterns, the shielding grid patterns are disposed on thetrench isolation such that the shielding grid patterns completely shieldthe trench isolation surrounding the image sensing units and partiallyshield the trench isolation surrounding the at least one phase detectionunit. The interconnection layer is disposed on the image sensing unitsand the at least one phase detection unit.

In accordance with yet alternative embodiments of the presentdisclosure, a method for fabricating an image sensor includes at leastthe following steps. A substrate having a plurality of active areasseparated from each other is provided. A plurality of image sensingunits and at least one phase detection unit are formed in the activeareas, and a size of each of the image sensing units is larger than asize of the at least one phase detection unit. An interconnection layeris formed on the substrate. A trench isolation is formed between twoadjacent active areas. A shielding material layer is patterned to form ashielding grid layer over the substrate opposite to the interconnectionlayer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. An image sensor, comprising: a substrate; a trench isolation in the substrate, wherein a plurality of active areas of the substrate are separated from each other by the trench isolation; a plurality of image sensing units; at least one phase detection unit, wherein the image sensing units and the at least one phase detection unit are in the active areas arranged in an array, and a sensing area of the at least one phase detection unit is smaller than a sensing area of each of the image sensing units; an interconnection layer, disposed below the image sensing units and the at least one phase detection unit; and a shielding grid layer over the trench isolation, wherein the shielding grid layer comprises a plurality of openings having substantially a same area, the sensing area of each of the image sensing units is equal to the area of the openings, and the sensing area of the at least one phase detection unit is smaller than the area of the openings.
 2. The image sensor according to claim 1, wherein the trench isolation comprises a plurality of first trench isolation patterns adjacent to each of the image sensing units and at least one second trench isolation pattern adjacent to the at least one phase detection unit, and an area occupied by the second trench isolation pattern is larger than an area occupied by the first trench isolation pattern.
 3. The image sensor according to claim 1, further comprising a dielectric layer, disposed between the shielding grid layer and the trench isolation.
 4. The image sensor according to claim 1, wherein a material of the shielding grid layer comprises tungsten or aluminum.
 5. The image sensor according to claim 1, wherein the substrate has a thickness of about 1.5 μm to about 3 μm.
 6. The image sensor according to claim 1, further comprising a plurality of micro-lenses disposed over the shielding grid layer.
 7. The image sensor according to claim 1, wherein the image sensing units and the at least one phase detection unit are photodiodes.
 8. An image sensor, comprising: a substrate; a trench isolation in the substrate, wherein a plurality of active areas of the substrate are separated from each other by the trench isolation; a plurality of image sensing units; at least one phase detection unit, wherein the image sensing units and the at least one phase detection unit are in the active areas arranged in an array; a shielding grid layer, comprising a plurality shielding grid patterns, a plurality of first openings above the image sensing units, and a second opening above the at least one phase detection unit, wherein each of the first openings is separated from the second opening by the shielding grid patterns, a sensing area of each of the image sensing units is equal to an area of each of the first openings, and a sensing area of the at least one phase detection unit is smaller than an area of the second opening; and an interconnection layer, disposed below the image sensing units and the at least one phase detection unit.
 9. The image sensor according to claim 8, wherein the shielding grid patterns are not overlapped with the image sensing units and the at least one phase detection unit.
 10. The image sensor according to claim 8, wherein the trench isolation comprises a plurality of first trench isolation patterns adjacent to each of the image sensing units and at least one second trench isolation pattern adjacent to the at least one phase detection unit, and the shielding grid patterns completely shield the first trench isolation patterns and partially shield the at least one second trench isolation pattern.
 11. The image sensor according to claim 8, further comprising a dielectric layer, disposed between the shielding grid layer and the trench isolation.
 12. The image sensor according to claim 8, wherein a material of the shielding grid layer comprises tungsten or aluminum.
 13. The image sensor according to claim 8, wherein the substrate has a thickness of about 1.5 μm to about 3 μm.
 14. The image sensor according to claim 8, further comprising a plurality of micro-lenses disposed over the shielding grid layer.
 15. The image sensor according to claim 8, wherein the image sensing units and the at least one phase detection unit are photodiodes.
 16. The image sensor according to claim 8, wherein the substrate is a silicon substrate, and a portion of the silicon substrate is located between the first openings and the image sensing units.
 17. A method of fabricating an image sensor, comprising: providing a substrate having a plurality of active areas separated from each other, the substrate comprising a first surface and a second surface opposite to the first surface; forming a first trench isolation in the substrate, wherein the first trench isolation has a plurality of openings accommodating the active areas and a depth of the first trench isolation is smaller than a thickness of the substrate; forming a plurality of image sensing units and at least one phase detection unit in the openings, wherein a size of each of the image sensing units is larger than a size of the at least one phase detection unit; forming an interconnection layer on the first surface of the substrate; after forming the first trench isolation, forming a plurality of trenches extending from the second surface of the substrate to the first trench isolation and filling a dielectric material in the trenches to form a second trench isolation, wherein the second trench isolation penetrates the substrate; and forming a shielding grid layer over the substrate opposite to the interconnection layer.
 18. The method of fabricating an image sensor according to claim 17, further comprising: forming the image sensing units and the at least one phase detection unit in the active areas.
 19. The method of fabricating an image sensor according to claim 17, further comprising: forming a dielectric layer between the substrate and the shielding grid layer; and forming a plurality of micro-lenses over the shielding grid layer.
 20. The method of fabricating an image sensor according to claim 17, wherein the interconnection layer comprises at least one trace layer, and/or a bonding substrate. 